The present invention relates to semiconductor integrated circuits and, more particularly, to a 5V tolerant PCI tri-state input-output (I/O) buffer which is fabricated on 2.5 technology and drives a 3.3V output signal without exceeding transistor tolerances.
CMOS integrated circuits are typically provided with tri-state I/O buffers that are selectively operable between a normal drive mode and a tri-state or high impedance mode in which the buffers appear transparent to the output terminals with which they are connected. Advancements in semiconductor fabrication technology enable the geometries of semiconductor devices to be progressively reduced so that more devices can fit on a single integrated circuit. As a result, core voltages of integrated circuits are being reduced to prevent damage to the small devices and to reduce overall power consumption. For example, power supplies are now being reduced from 5V to 3.3V, and from 3.3V to 2.5V.
However, low voltage CMOS devices are often interconnected at a board level to TTL logic and other devices that operate at higher supply voltages of 5V or 3.3V. For example, buffer specifications for peripheral component interfaces (PCIs) require the buffers to be tolerant to input signals having the steady state PCI voltage, such as 5V, and voltage spikes that are twice that of ten percent greater than the PCI voltage, or 11V for a 5V PCI voltage.
Diodes have been placed on the pad terminals of I/O buffers to clamp input spikes at or near the worst case PCI voltage, such as about 5.5V for a 5V PCI. If no further precautions are taken, a clamped 5.5V signal applied to the pad terminal of a 2.5V tri-state output buffer can cause voltage drops across the transistor devices in the buffer that exceed the transistor tolerances, which can cause the gate oxide of the devices to breakdown. It is therefore desirable to provide an I/O buffer that is tolerant to large pad voltages without exceeding the tolerance levels of the devices within the buffer.